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Computer Architecture Interview Questions

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As superscalar machines become more complex the difficulties of scheduling instruction issue become more complex. Another way of looking at superscalar machines is as dynamic instruction schedulers - the hardware decides on the fly which instructions to execute in parallel out of order etc. An alternative approach would be to get the compiler to do it beforehand - that is to statically schedule execution. This is the basic concept behind Very Long Instruction Word or VLIW machines.

write-back cache a caching method in which modifications to data in the cache aren't copied to the cache source until absolutely necessary. write-through cache performs all write operations in parallel -- data is written to main memory and the L1 cache simultaneously. Write-back caching yields somewhat better performance than write-through caching because it reduces the number of write operations to main memory. With this performance improvement comes a slight risk that data may be lost if the system crashes.

The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.Latches are asynchronous, which means that the output changes very soon after the input changes.A flip-flop is a synchronous version of the latch. Latch is a level sensitive device and flip-flop is edge sensitive device. Latch is sensitive to glitches on enable pin, where as flip-flop is immune to gltiches. Latches take less gates (also less power) to implement then flip-flops. Latches are faster then flip-flops. this is how the output of the two will differ: the output of the latch will be the same as the data input as it does not have a clock signal whereas in a flipflop there would be a delay of one clock cycle to see the output.

A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address storage unit storing a return address to be generated depending on an execution result of the call instruction, and a branch prediction address storage unit sending a stored prediction return address as a branch prediction address and storing the sent branch prediction address. When the branch prediction address differs from a return address, which is generated after executing a branch instruction or a return instruction, contents stored in the second return address storage unit are copied to the first return address storage unit.

Each place in cache records block's tag (as well as its data). Of course place in cache may be unoccupied so usually place maintains valid bit. So to find block in cache: 1. Use index of block address to determine place (or set of places) 2. For that (or each) place check valid bit is set and compare tag with that of block address --- this can be done in parallel for all places in a set.

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