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The Transmission-Gate's input is connected to the D_LATCH data input (D), the control input to the Transmission-Gate is connected to the D_LATCH enable input (EN) and the Transmission-Gate output is the D_LATCH output (Q) 

Use the concept of register-retiming.
divide the total combinatorial delay in two segments such that individually the delay is less the clock period.
this can be done by inserting a flip-flop in the combinational path.
e.g,
clock period --- 5 ns
total cominational delay ---- 7
then divide the 7ns path in two path of 4 or 3 (best results are obtained if delays are same for both path i.e 3.5ns) by inserting a flip-flop in between. 

Sequence detector : A sequence detector gives an output of 1 on detecting the given sequence else the output is zero.

Ex : if the given sequence to be detected is 111
and input stream is 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1
the output should be 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1.

Soln:
One of the different possible ways to detect a sequence is using a Mealy type FSM.

Using the following table the State machine can be designed.
since the number of bits in the sequence 1101 is 4 we have 4 states

------------------------------------------------------
|PS | Seq detected by the state | NS/output |
| | |---------------|
| | | X=0 | X=1 |
|-----------------------------------------------------
| S1 | - | S1/0 | S2/0 |
|----------------------------------------------------|
| S2 | 1 | S1/0 | S3/0 |
|----------------------------------------------------|
| S3 | 11 | S4/0 | S3/0 |
|----------------------------------------------------|
| S4 | 110 | S1/0 | S2/1 |
|----------------------------------------------------|

when in state S4 (PS),and input(X) from the sequence is 1,the sequence "1101" has been detected once and (to find the next state select the longest "seq identified by a state" column that matches part of the sequence 1101--ie.,1 or 01 or 101 ....)the NS is S2 since the sequence detected by the state S2 is 1(in 1101- 01 or 101 ,etc are not present in the seq identified by the state column ,) 

TRUTH TABLE FOR HALF ADDER:

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

IMPLEMENTATION:

For SUM, The two inputs A and B are given to XOR gate.

For Carry, The two inputs A and B are given to AND gate. 

Take a smiths counter with 3 f/f's
that is to say with 6 states(2*3)
now double the i/p clock frequency to the counter
the o/p of the 3rd f/f is divide by 6 of the i/p with 50% duty cycle
so effectively u got divide by 3 freq with 50% duty cycle 

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